The 7nm Surprise

In September 2023, a phone went on sale in China and quietly upended a debate about the limits of US sanctions. Teardown specialists at TechInsights pulled apart Huawei’s Mate 60 Pro and found, inside it, a processor, the Kirin 9000S, built by China’s top foundry SMIC on a 7nm-class process, without a single EUV lithography machine.^[1]

That last part is the story. Extreme-ultraviolet (EUV) lithography, made only by the Netherlands’ ASML, is the tool the industry uses for advanced chips, and it has been barred from China throughout. SMIC reached 7nm anyway, using older deep-ultraviolet (DUV) scanners and a painstaking technique called multi-patterning, exposing each layer several times to draw finer features than the light should allow.^[1] As TechInsights put it, the chip “demonstrates the technical progress China’s semiconductor industry has been able to make without EUV.”^[1]

Impressive, and capped

It was a genuine milestone with real limits. TechInsights judged DUV “perfectly capable of 7nm,” but warned that pushing multi-patterning toward 5nm and 3nm carries steep “yield and cost penalties.”^[2] Reports that SMIC is working toward 5nm on DUV come with unverified estimates of yields a fraction of TSMC’s and cost premiums around 50%; figures SMIC does not disclose, and which should be read as estimates, not facts.^[3] SMIC is nonetheless China’s largest foundry and among the world’s top three by revenue, with a record roughly $8 billion in 2024.^[4]

China built a 7nm smartphone chip with 1980s-era light. Sanctions delayed the climb; they did not cap it — yet.

The right way to hold the 7nm milestone is as evidence of both capability and constraint at once. Multi-patterning proves that a determined, well-funded foundry can reach a node the tools were not meant to reach, but it does so by exposing each layer several times, which multiplies process steps, defect opportunities and cost per wafer. That penalty is manageable at 7nm and grows punishing toward 5nm and 3nm, which is exactly why the bottleneck has migrated from the chip to the lithography that makes it. A node reached at ruinous yield is a demonstration; a node reached at a workable cost is a business, and only the second changes the competitive map.

The part that matters

The 7nm surprise reframed the debate from “can China reach the leading edge?” to “at what cost, and how far?” Multi-patterning buys nodes at the price of yield and economics, which is precisely why the constraint has migrated from the chip to the tools that make it (see our companion briefs on lithography and equipment). We treat SMIC’s node claims as directional and unverified until a teardown confirms them, and we watch the metric that actually decides competitiveness: not whether a node can be reached, but whether it can be produced at a yield and cost that make sense.