The most powerful chokepoint in semiconductors is not a machine or a material. It is software. No advanced chip is designed without electronic design automation (EDA) tools, and three companies, Synopsys, Cadence and Germany’s Siemens EDA, control more than 85% of that market worldwide, and over 70% inside China.[1] At the leading edge the grip is tighter still: a modern chip carries tens of thousands of design rules no human can manage, verification consumes most of the design cycle, and foundries mandate specific tools for tape-out.[1]
In 2025, Washington demonstrated the leverage, and its limits. In late May, US export authorities required licences for EDA sales to China, hitting all three vendors.[2] Roughly six weeks later, on 2 July, the restriction was rescinded as part of a trade truce tied to rare-earth access.[3] The chokepoint was real enough to rattle markets (China is a low-double-digit share of Synopsys and Cadence revenue) and, this time, one Washington chose not to hold.[2][3]
The domestic answer is partial
China’s EDA champions cover only parts of the design flow. Empyrean (Huada) leads domestically, strongest in analog and full-custom design, and in 2025 unveiled a full-process platform for memory chips; Primarius specialises in device modelling, Semitronix in yield tools.[1] But no Chinese vendor offers a complete, verified digital-design flow at 7nm and below — domestic tools win mainly at mature nodes, and claims of advanced-node support rest largely on company statements rather than independent confirmation.[1]
Three firms gate the design of nearly every advanced chip on Earth. Washington flipped that switch on and off in six weeks.
EDA is the highest-leverage chokepoint in the entire stack for a reason that has nothing to do with capital: the tools are sequential and lock-in is near-total, so a single mandated signoff tool gates an entire tape-out, and swapping one forces re-running everything downstream. That is why three firms can hold a market a fraction the size of the equipment industry yet exert more control than any single machine maker. The 2025 on-off also revealed the limit of the leverage: a chokepoint this disruptive is now a bargaining chip in a broader negotiation, which means its use is governed as much by trade politics as by security, a variable, not a wall.
What we do with this
EDA is the highest-leverage, lowest-capital chokepoint in the entire stack, which is what makes both the US restriction and China’s scramble to replace it so consequential. The near-term reality is dependence: the domestic tools are progressing at mature nodes but are years from a full leading-edge flow. We treat EDA localisation as a long project to track vendor by vendor and node by node, and the on-off of 2025 as a reminder that these controls are now bargaining chips, not just barriers.
| Ref | Publication | Date | Supports |
|---|---|---|---|
| [1] | SemiAnalysis | 2025 | Market shares, lock-in, domestic vendor coverage |
| [2] | South China Morning Post | Jun 2025 | May 2025 licence requirement and China revenue exposure |
| [3] | CNN Business | Jul 2025 | Rescission of the curbs on 2 July 2025 |
References
- SemiAnalysis, “EDA Market Primer,” 2025. Read source ↗
- South China Morning Post, “Tech war: China’s top three EDA firms under spotlight after US ban on chip design tools,” Jun 2025. Read source ↗
- CNN Business, “US lifts chip design software curbs against China following London trade talks,” Jul 2025. Read source ↗
Every source above is public and linked. This is a research brief from Singularity Dynamics; full briefings on this topic are available on request.