Stacking, Not Shrinking

If you cannot make the transistors smaller, put more chips together. That, in one line, is China’s most effective workaround for the lithography wall, and Huawei has turned it into a strategy.

Denied the leading-edge nodes that let rivals pack more onto a single die, Huawei’s AI accelerators reportedly stack multiple 7nm-class chiplets in one package to roughly double the compute.^[1] The system-level result is genuinely striking: analysts estimate Huawei’s CloudMatrix 384, which wires together 384 of its Ascend chips, out-throughputs Nvidia’s flagship 72-GPU system by around 1.7 times.^[1] It gets there by brute force, drawing nearly four times the power, but at the system level, it competes.^[1]

What packaging can and cannot do

The workaround has hard limits, and honesty about them matters. Packaging raises performance per package; it does not shrink a transistor, so China still pays in die area, power and yield.^[1] And the binding constraint has moved to memory: by one analysis, China’s stockpile of high-bandwidth memory, not its supply of logic dies, is what caps how many accelerators it can actually build.^[2] The performance figures are careful analyst estimates, not Huawei disclosures, and the most advanced designs are so far patents, not shipping products.^[3] Meanwhile China’s packaging houses are already world-class: JCET ranks third globally and Tongfu fourth, and Tongfu has filed dozens of hybrid-bonding patents.^[4]

Can’t shrink the transistor? Stack the silicon. China is brute-forcing AI performance by packaging, not scaling, and paying for it in watts.

Packaging is best understood as buying performance with a different currency. Where a smaller transistor delivers more compute per watt and per square millimetre, stacking delivers more compute per package while the underlying silicon stays on an older node — so the gains are paid for in die area, power and yield. At the system level that trade can be won, as a cluster that out-throughputs a rival while drawing several times the power demonstrates. But it relocates the bottleneck rather than removing it, and the new binding constraint is high-bandwidth memory, not logic. The strength is real and China’s packaging houses are global leaders; the ceiling is real too.

The consequence for portfolios

Advanced packaging is the single most important reason China can compete in AI hardware despite the node gap, and one of the few layers where its OSAT firms are already global leaders, not challengers. It is a real, investable strength. But it narrows the gap; it does not close it, and it shifts the bottleneck to memory. We track the packaging leaders and the hybrid-bonding roadmap as a genuine edge, while pricing in the power, yield and memory constraints that packaging cannot engineer away.